19 Commits

Author	SHA1	Message	Date
Roman Zeyde	728919ee2f	pylint common.py	2014-07-22 14:20:02 +03:00
Roman Zeyde	8a6a9ed042	test 16kB with 40kbps = 10 freqs x QAM16	2014-07-22 14:20:02 +03:00
Roman Zeyde	cbf8cddabb	44kbps on 128KB	2014-07-22 14:19:52 +03:00
Roman Zeyde	2e4718e0fe	40kbps demo	2014-07-22 14:19:52 +03:00
Roman Zeyde	fa40381248	common: add capture for iterator results	2014-07-22 14:19:52 +03:00
Roman Zeyde	9981f280f4	parallel iterator split	2014-07-22 14:19:52 +03:00
Roman Zeyde	140011406b	move DSP stuff to sigproc	2014-07-22 14:19:51 +03:00
Roman Zeyde	a5571d13d0	fix common.load()	2014-07-22 14:19:50 +03:00
Roman Zeyde	818ca9e8e4	fix to_bytes()	2014-07-22 14:19:50 +03:00
Roman Zeyde	656b5120a5	remove unneeded print	2014-07-22 14:19:50 +03:00
Roman Zeyde	40915f4f15	Refactor iteration.	2014-07-22 14:19:50 +03:00
Roman Zeyde	5a854be751	Refactor a bit	2014-07-22 14:19:50 +03:00
Roman Zeyde	b276440b01	remove Signal class.	2014-07-22 14:19:50 +03:00
Roman Zeyde	c0cb186d87	Remove unused code	2014-07-22 14:16:50 +03:00
Roman Zeyde	942a52872a	Add RS ECC	2014-07-22 14:16:48 +03:00
Roman Zeyde	fbbc404b45	Use 4 carriers wit QAM16 to achieve 16kbps.	2014-07-22 14:16:41 +03:00
Roman Zeyde	5c6304823d	Use 2 frequencies to achieve 8kbps	2014-07-22 14:16:33 +03:00
Roman Zeyde	b15f891aa0	Reorganize code.	2014-07-22 14:16:00 +03:00
Roman Zeyde	bc067c8bbd	Add QPSK16 modem	2014-06-19 17:59:51 +03:00