62 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Roman Zeyde	fbb922f4ee	README.md edited online with Bitbucket	2014-07-22 14:19:51 +03:00
Roman Zeyde	443217a51d	refactor training	2014-07-22 14:19:51 +03:00
Roman Zeyde	e2bba5c298	fix rx file at recv.py	2014-07-22 14:19:51 +03:00
Roman Zeyde	6bb3fa9767	fix calibration	2014-07-22 14:19:51 +03:00
Roman Zeyde	599f3858fd	add drift calculation on carrier	2014-07-22 14:19:51 +03:00
Roman Zeyde	7f382d68d4	better subplot	2014-07-22 14:19:51 +03:00
Roman Zeyde	25e895029d	move extract_symbols() to sigproc	2014-07-22 14:19:51 +03:00
Roman Zeyde	a0389f2144	rename iterator	2014-07-22 14:19:51 +03:00
Roman Zeyde	62b7c44ddb	refactor receiver for open-loop resampling	2014-07-22 14:19:51 +03:00
Roman Zeyde	881798b30b	fix sampling UT	2014-07-22 14:19:51 +03:00
Roman Zeyde	24ed672cf9	fix prefix size, for identity interpolation at integer offsets	2014-07-22 14:19:51 +03:00
Roman Zeyde	1534e13bd6	add logger sampling	2014-07-22 14:19:51 +03:00
Roman Zeyde	db5908d63f	refactor sigproc	2014-07-22 14:19:51 +03:00
Roman Zeyde	c001650bbf	fix FreqLoop itertools usage	2014-07-22 14:19:51 +03:00
Roman Zeyde	933e0f7cfc	support concurrent multiple frequencies demodulation.	2014-07-22 14:19:51 +03:00
Roman Zeyde	8a1d8f33bd	split demodulation using itertools.tee()	2014-07-22 14:19:51 +03:00
Roman Zeyde	63fbee8bfc	Add test for sampling	2014-07-22 14:19:51 +03:00
Roman Zeyde	c9d7f8e2f2	refactor loop	2014-07-22 14:19:51 +03:00
Roman Zeyde	c1302a2d82	work on iterator decoding	2014-07-22 14:19:51 +03:00
Roman Zeyde	5b4c1fe32b	return None if not blocks decoded.	2014-07-22 14:19:51 +03:00
Roman Zeyde	9f422cd4ac	fix plotting	2014-07-22 14:19:51 +03:00
Roman Zeyde	140011406b	move DSP stuff to sigproc	2014-07-22 14:19:51 +03:00
Roman Zeyde	20d31b68fb	move constellation() to show.py	2014-07-22 14:19:51 +03:00
Roman Zeyde	cb7e237434	pylab.show() if environment variable SHOW is set	2014-07-22 14:19:50 +03:00
Roman Zeyde	f740cae064	test recv on 3ppm error.	2014-07-22 14:19:50 +03:00
Roman Zeyde	b49954a7e1	add sampling script invocation	2014-07-22 14:19:50 +03:00
Roman Zeyde	5e30d47f78	add constellation for debugging	2014-07-22 14:19:50 +03:00
Roman Zeyde	286fe9010e	add assertion to ECC	2014-07-22 14:19:50 +03:00
Roman Zeyde	a5571d13d0	fix common.load()	2014-07-22 14:19:50 +03:00
Roman Zeyde	1fe05dfe63	refactor sampling	2014-07-22 14:19:50 +03:00
Roman Zeyde	50ffdfb1dd	refactor recv	2014-07-22 14:19:50 +03:00
Roman Zeyde	2e2ebd6280	refactor sigproc	2014-07-22 14:19:50 +03:00
Roman Zeyde	4753797136	remove mean subtraction	2014-07-22 14:19:50 +03:00
Roman Zeyde	cabf215d1f	Fix detect.	2014-07-22 14:19:50 +03:00
Roman Zeyde	818ca9e8e4	fix to_bytes()	2014-07-22 14:19:50 +03:00
Roman Zeyde	8a1a9f2377	Refactor frequency loop as a generator.	2014-07-22 14:19:50 +03:00
Roman Zeyde	2c9cec24eb	add loop module	2014-07-22 14:19:50 +03:00
Roman Zeyde	3007ea3c9a	Frequency loop is working on real signal	2014-07-22 14:19:50 +03:00
Roman Zeyde	656b5120a5	remove unneeded print	2014-07-22 14:19:50 +03:00
Roman Zeyde	40915f4f15	Refactor iteration.	2014-07-22 14:19:50 +03:00
Roman Zeyde	4f5678f687	Add frequency resampling	2014-07-22 14:19:50 +03:00
Roman Zeyde	18000e4ebe	Add interpolation demo	2014-07-22 14:19:50 +03:00
Roman Zeyde	5d3d1c36fb	Move import ECC to calling function.	2014-07-22 14:19:50 +03:00
Roman Zeyde	8c6d046861	Add calibration script	2014-07-22 14:19:50 +03:00
Roman Zeyde	5a854be751	Refactor a bit	2014-07-22 14:19:50 +03:00
Roman Zeyde	b276440b01	remove Signal class.	2014-07-22 14:19:50 +03:00
Roman Zeyde	cf73a158a9	WIP	2014-07-22 14:19:50 +03:00
Roman Zeyde	d7e45bc9df	Add loop player.	2014-07-22 14:16:50 +03:00
Roman Zeyde	6f4d6e1f8d	Move wave play/record into separate module.	2014-07-22 14:16:50 +03:00
Roman Zeyde	12a1811b12	Fix typo.	2014-07-22 14:16:50 +03:00